The present invention relates to a method of simulating the operation of a semiconductor device by using the mask layout patterns thereof, and more particularly to a circuit resistance calculating method suited to calculate the resistance value of a diffused region used as the source or drain region of a metal oxide semiconductor field effect transistor (hereinafter referred to as "MOSFET").
Two methods have been known for calculating the resistance value of a resistive area pattern (that is, a pattern showing a resistive area). One of the methods is called a potential method, in which the two-dimensional potential distribution in the resistive area pattern is determined through numerical analysis techniques, to obtain the resistance value of the pattern. (Refer to an article entitled "LAS: LAYOUT PATTERN ANALYSIS SYSTEM WITH NEW APPROACH" by Yoshio Okamura et al., Proc. of IEEE ICCC, 1982, pages 308 to 311, and "EXCL: A Circuit Extractor for IC Designs" by Steven P. McCormik, 21st Design Automation Conf. Proceedings, pages 616 to 623, 1984). The other methods are called a center line method or rectangular decomposition method, in which the direction of current flowing through a resistive area is first determined, and the resistance value of the resistive area is calculated from the length of the area along the current direction and the width of the area in a direction perpendicular to the current direction. (Refer to an article entitled "A MASK VERIFICATION SYSTEM FOR BIPOLAR IC" by J. Yoshida et al., 18th Design Automation Conf. Proceedings, pages 690 to 695, June, 1981 and "Resistance Extraction in a Hierachical IC Artwork Verification System" by S. Mori et al., Proc. of IEEE ICCAD, 1985, pages 196 to 198).
The potential method is applicable to the calculation of the resistance value of the diffused source or drain region of a MOSFET, but has the following drawback. That is, a large storage capacity is required for the calculation, and a long calculation time is necessary. Thus, a cost for calculating resistance values of a multiplicity of resistive areas indicated by the mask pattern of an LSI becomes very high. While, the center line method is and the rectangular decomposition method are low in calculation cost, but have a disavantage that it is impossible to calculate the resistance value of a resistive area contiguous to a high-resistance area far larger in resistance value than the resistive area, that is, it is impossible to calculate the resistance value of the diffused source or drain region of a MOSFET contiguous to a channel having a large resistance value.